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s3c8618/c8615/p8615 product overview 1- 1 1 product overview sam8 product family samsung's sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. important cpu features include: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. s3c8618/c8615/p8615 microcontroller s the s3c8618/c8615/p8615 single-chip 8-bit microcontroller is based on the powerful sam8 cpu architecture. the internal register file is logically expanded to increase the on-chip register space. the s3c8618/c8615/p8615 ha ve 8/16 k bytes of on-chip program rom. following samsung's modular design approach, the following peripherals were integrated with the sam8 core: ? f our programmable i/o ports (total 28 pins) ? one 8-bit basic timer for oscillation stabilization and watchdog functions ? one 8-bit general-purpose timer/counter with selectable clock sources ? one 8-bit counter with selectable clock sources, including hsync or csync input ? one 8-bit timer for interval mode ? pwm block with seven 8-bit pwm circuits ? sync processor block (for vsync and hsync i/o, csync input, and clamp signal output) ? multi master iic-bus with ddc support. the s3c8618/c8615/p8615 are a versatile microcontroller that is ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, pwm, sync signal processing, and multi-master iic-bus support with ddc. it is available in a 42-pin sdip or a 44 -pin qfp package. figure 1-1. s3c8618/c8615/p8615 m icrocontroller s
product overview s3c8618/c8615/p8615 1- 2 features cpu ? sam8 cpu core memory ? 8/ 16-kbyte internal program memory (rom) ? 272-byte genera l-purpose register area instruction set ? 78 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 500 ns minimum (with 12 mhz cpu clock) interrupts ? nine interrupt sources ? nine interrupt vectors ? six interrupt levels ? fast interrupt processing for a select level general i/o ? four i/o ports (total 28 pins): 8-bit basic timer ? programmable timer for oscillation stabilization interval control or watchdog timer functions ? three selectable internal clock frequencies timer/counters ? one 8-bit general-purpose timer/counter with programmable operating modes and the following clock source options: ? t wo selectable internal clock frequencies ? one 8-bit timer with interval operating mode ? one 8-bit counter with the following clock source options: ? two selectable internal clock frequencies ? hsync (or csync) input from the sync processor block ? external clock source pulse width modulator ? seven 8-bit pwm modules: ? 8-bit basic frame ? four push-pull and three n-channel, open-drain output channels ? selectable clock frequencies: 46.875 khz at 12 mhz fosc. sync processor ? detection of sync input signals (vsync-i, hsync-i, and csync-i) ? sync signal separation and output (hsync-o, vsync-o, and clamp-o) ? pseudo sync signal output ? programmable clamp signal output ddc and multi-master iic-bus ? serial peripheral interface ? support for display data channel (ddc) oscillator frequency ? 6 mhz to 12 mhz external crystal oscillator ? interval max. 12mhz cpu clock operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 4.5 v to 5.5 v package types ? 42-pin sdip, 44-pin qfp
s3c8618/c8615/p8615 product overview 1- 3 block diagram reset p1.0?p1.3 x in x out main osc p3.0?p3.7 internal bus p2.0?p2.7 port 0 p0.0?p0.7/int0-int2 port 2 8-bit pwm (7-ch) sync pro- cessor timer 0 port 1 port3 pwm0 pwm1 ? ? ? pwm6 vsync-i hsync-i csync-i vsync-o hsync-o clamp-o t0cap 8-blt counter ( timer 1) t1ck ddc and multi master iic-bus scl sda int0-int2 test interval timer ( timer 2) sam8 cpu 8/16 -kbyt e mask rom 272-byte register file i/o port and interrupt control figure 1-2. block diagram
product overview s3c8618/c8615/p8615 1- 4 pin assignments p3.1 p3.0 p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/t0cap p0.5/t1ck v dd p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.2 v ss2 p3.3 p3.4 p3.5 p3.6 p3.7 reset x out x in v ss1 p2.7/csync-i hsync-i vsync-i (vclk) clamp-o hsync-o vsync-o scl sda test p2.6/pwm6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 s3c8618/8615 42-sdip (top view) figure 1-3. pin assignment diagram (42-sdip package)
s3c8618/c8615/p8615 product overview 1- 5 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 n.c. p2.6/pwm6 test sda scl vsync-o 1 2 3 4 5 6 7 8 9 10 11 hsync-o clamp-o vsync-i hsync-i p2.7/csync-i v ss1 x in x out reset p3.7 p3.6 s3c8618/8615 44-qfp (top view) p0.2/int2 p0.1/int1 p0.0/int0 p3.0 p3.1 nc p3.2 v ss2 p3.3 p3.4 p3.5 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 44 43 42 41 40 39 38 37 36 35 34 p2.0/pwm0 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 v dd p0.5/t1ck p0.4/t0cap p0.3 figure 1-4. pin assignment diagram (44-qfp package)
product overview s3c8618/c8615/p8615 1- 6 pin descriptions table 1-1. s3c8618/c8615/p8615 pin descriptions pin names pin type pin description circuit type sdip pin numbers shared functions p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 i/o general-purpose, 8-bit i/o port. share functions include three external interrupt inputs, i/o for timers 0 and 1. you can selectively configure port 0 pins to input or output mode. d- 1 3 4 5 6 7 8 10 11 int0 int1 int2 t0cap t 1ck p1.0 ? p1. 3 i/o general purpose, 8-bit i/o port. you can selectively configure port 1 pins to input or push-pull output mode . d-1 12?1 5 ? p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 i/o general purpose, 8-bit i/o port. you can selectively configure port 2 pins to input or output mode. the port 2 pin circuit are designed to push-pull pwm output and csync signal input . d-1 d-1 d-1 d-1 e-1 e-1 e-1 d-1 16 17 18 19 20 21 22 31 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 csync-i p3.0?p3.7 i/o general-purpose, 8-bit i/o port. you can selectively configure port 3 pins to input or output mode. e 2, 1, 42, 40?36 ? hsync - i vsync - i c lamp- o hsync - o vsync - o scl sda i i o o o i/o i/o the pins are sync processor signal i/o and iic-bus clock and data i/o a a a a a g-3 g-3 30 29 28 27 26 25 24 ? v dd v ss1 , v ss2 ? power supply pins ? 9 32, 41 ? x in , x out ? system clock input and output pins ? 33, 34 ? reset i system reset pin b 35 ? test i factory test pin input 0 v: normal operation 5 v: factory test mode ? 23 ? note : see ?pin circuit diagrams? on next two pages for detailed information on circuit types a, b, d-1, e, e-1,and g-3 .
s3c8618/c8615/p8615 product overview 1- 7 pin circuits v ss v dd figure 1-5. pin circuit type a v dd noise filter 280 k w reset figure 1-6. pin circuit type b ( reset reset ) output v ss v dd output disable data or other function digital input or ttl input figure 1-7. pin circuit type d-1
product overview s3c8618/c8615/p8615 1- 8 typical 47-k w data v dd output p ull-up enable input v ss open drain output disable v dd figure 1-7. pin circuit type e output disable data in/out input v ss open drain v dd figure 1-8. pin circuit type e-1
s3c8618/c8615/p8615 product overview 1- 9 data output input v ss figure 1-9. pin circuit type g-3
s3c8618/c8615/p8615 electrical data 16 - 1 16 electrical data overview in this section, s3c8618/c8615 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? i/o capacitance ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? schmitt trigger characteristics
electrical data s3c8618/c8615/p8615 16 - 2 table 16 -1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 7.0 v input voltage v i 1 type c (n-channel, open-drain) ? 0.3 to + 10 v v i2 all port pins except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 60 output current low i ol1 one i/o pin active + 30 ma i ol2 total pin current except port 3 + 100 i ol3 sync-processor i/o pins and iic-bus clock and data pins + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 16- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v v ih2 x in , x out v dd ? 0.5 v dd v ih3 ttl input (hsynci, vsynci and csynci) 2.0 v dd input low voltage v il1 all input pins except v il2 and v il3 ? ? 0.2 v dd v v il2 x in , x out 0.4 v il3 ttl input (hsynci, vsynci and csynci) 0.8 output high voltage v oh1 v dd = 4.5 v to 5.5 v i oh = ? 8 ma port 1 only v dd ? 1.0 ? ? v v oh2 v dd = 4.5 v to 5.5 v i oh = ? 2 ma ports 0, 2, clampo, h and vsynco v dd ? 1.0 v oh3 v dd = 4.5 v to 5.5 v i oh = ? 6 ma , port 3 v dd ? 1.0
s3c8618/c8615/p8615 electrical data 16 - 3 table 16- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 8 ma, port 1 only ? ? 0.4 v v ol2 i ol = 2 ma port 0, 2, clampo, h synco and vsynco 0.4 v ol3 i ol = 6 ma port 3, scl and sda 0.4 input high leakage current i lih1 v in = v dd all input pins except x in , x out ? ? 3 a i lih2 v in = v dd x out only ? ? 20 i lih3 v in = v dd x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 a i lil2 v in = 0 v; x out only ? ? ? 20 i lil3 v in = 0 v; x in only ? 2.5 ? 6 ? 20 output high leakage current i lohl v out = v dd all output pins except port 1 ? ? 3 a output low leakage current i lol v out = 0 v ? ? ? 3 a pull-up resistor r l1 v in = 0 v; v dd = 4.5 v to 5.5 v port 3 20 47 80 k w r l2 v in = 0 v; v dd = 4.5 v to 5.5 v reset only 150 280 480 supply current (note ) i dd1 v dd = 4.5 v to 5.5 v 12 mhz cpu clock ? 15 30 ma i dd2 idle mode; v dd = 4.5 v to 5.5 v 12 mhz cpu clock 5 1 0 i dd3 stop mode; v dd = 5.0 v 1 10 a note : supply current does not include drawn internal pull?up resistors and external loads of output.
electrical data s3c8618/c8615/p8615 16 - 4 table 16- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 6 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a notes : 1. during the oscillator stabilization wait time (t wait ), all cpu operations must be stopped. 2. supply current does not include drawn through internal pull?up resistors and external output current loads. v dd reset execution of stop instruction v dddr data retention mode stop mode reset occurs normal operating mode oscillation stabilization time t wait note : t wait is the same as 4096 32 1 / f osc . ? ? figure 16-1 . stop mode release timing when initiated by a reset table 16- 4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
s3c8618/c8615/p8615 electrical data 16 - 5 table 16- 5. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.5 v to 5.5v) parameter symbol conditions min typ max unit noise filter t nf1h , t nf1l p0.2? p0.0, t0cap and t1ck (rc delay) 300 ? ? ns t nf2 reset only (rc delay) 800 ? ? 1 t cpu t nf1l t nf1h 0.8 v dd t nf2 0.2 v dd note : the unit t cpu means one cpu clock period. figure 16- 2. input timing measurement points for p0.0? p0.2, t0cap and t1ck
electrical data s3c8618/c8615/p8615 16 - 6 table 16-6. oscillation characteristics (t a = ? 40 c + 85 c) oscillator clock circuit conditions min typ max unit main crystal or ceramic c2 c1 x in x out v dd = 4.5 v to 5.5 v 6 ? 12 mhz external clock (main) x in x out v dd = 4.5 v to 5.5 v 6 ? 12 mhz note: the maximum oscillator frequency is 12 mhz. if you use an oscillator frequency higher than 12 mhz, you cannot select a non-divided cpu clock using clkcon settings. that is, you must select one of the divide-by values. table 16-7 . recommended oscillator constants (t a = ? 40 c + 85 c, v dd = 4.5 v to 5.5 v) manufacturer product name load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr8.0mc5 (note) ? ? 4.5 5.5 on-chip c leaded type fcr8.0m5 33 33 4.5 5.5 leaded type ccr8.0mc5 (note) ? ? 4.5 5.5 on-chip c smd type note : on-chip c: 30 pf 20 % built in. table 16-8 . oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator test condition min typ max unit crystal v dd = 4.5 v to 5.5 v ? ? 20 ms ceramic v dd = 4.5 v to 5.5v ? ? 10 external clock x in input high and low level width (t xh , t xl ) 25 ? 500 ns note : o scillation stabilization time is the time required for the cpu clock to return to its normal oscillation frequency after a power-on occurs, or when stop mode is released.
s3c8618/c8615/p8615 electrical data 16 - 7 x in t xl t xh 1 / f osc v dd ? 0.5 v 0.4 v figure 16-3. clock timing measurement points for x in v dd v ss v out a b c d v in a : 0.2 v dd b : 0.4 v dd c : 0.6 v dd d : 0.8 v dd figure 16-4. schmitt trigger characteristics (normal port; except ttl input)
s3c8618/c8615/p8615 mechanical data 17 - 1 17 mechanical data overview the s3c8615 microcontroller is available in a 42-pin sdip package (samsung part number 42-sdip-600) and a 44 -qfp package (samsung part number 44-qfp-1010b). note : dimensions are in millimeters. 42-sdip-600 14.00 0.2 0.50 0.1 39.10 0.2 0 ~ 15 0.25 +0.1 ? 0.05 #1 21 42 22 15.24 (1.77) 1.00 0.1 1.778 0.51min 3.50 0.2 3.30 0.3 5.08max figure 17 -1. 42-pin sdip package mechanical data (42-sdip-600)
mechanical data s3c8618/c8615/p8615 17 - 2 note : dimensions are in millimeters. 44-qfp-1010b 13.20 0.3 #44 (1.00) #1 13.20 0.3 0.35 +0.10 - 0.05 0.10 max 0~8 0.05 min 2.05 0.10 2.30 max 0.80 0.20 0.15 +0.10 - 0.05 10.00 0.2 10.00 0.2 0.80 figure 17 -2. 44-pin qfp package mechanical data (44-qfp-1010b)
s3c8618/c8615/p8615 s3 p8615 otp 18- 1 18 S3P8615 otp overview the S3P8615 single-chip cmos microcontroller is the otp (one time programmable) version of the S3P8615 microcontrollers. it has an on-chip eprom instead of masked rom. the eprom is accessed by serial data format. the S3P8615 is fully compatible with the s3c8618/c8615, both in function and in pin configuration. because of its simple programming requirements, the S3P8615 is ideal for use as an evaluation chip for the s3c8618/c8615. p3.1 p3.0 p0.0/int0 p0.1/int1 p0.2/int2 p0.3 p0.4/t0cap p0.5/t1ck v dd /v dd p0.6 p0.7 sclk /p1.0 sdat /p1.1 p1.2 p1.3 p2.0/pwm0 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p3.2 v ss2/ v ss2 p3.3 p3.4 p3.5 p3.6 p3.7 reset/ reset reset x out x in v ss1/ v ss1 p2.7/csync-i hsync-i vsync-i (vclk) clamp-o hsync-o vsync-o scl sda test/ v pp p2.6/pwm6 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 s3p8618/8615 42-sdip (top view) note: the bolds indicate an otp pin name. figure 18-1. S3P8615 pin assignments (42-sdip package)
S3P8615 otp s3c8618/c8615/p8615 18- 2 p2.1/pwm1 p2.2/pwm2 p2.3/pwm3 p2.4/pwm4 p2.5/pwm5 n.c. p2.6/pwm6 v pp /test sda scl vsync-o 1 2 3 4 5 6 7 8 9 10 11 hsync-o clamp-o vsync-i hsync-i p2.7/csync-i v ss1 /v ss1 x in x out reset reset / reset p3.7 p3.6 s3c8618/8615 44-qfp (top view) p0.2/int2 p0.1/int1 p0.0/int0 p3.0 p3.1 nc p3.2 v ss2/ v ss2 p3.3 p3.4 p3.5 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 44 43 42 41 40 39 38 37 36 35 34 p2.0/pwm0 p1.3 p1.2 p1.1/ sdat p1.0/ sclk p0.7 p0.6 v dd/ v dd p0.5/t1ck p0.4/t0cap p0.3 figure 18-2. S3P8615 pin assignments (44-qfp package)
s3c8618/c8615/p8615 s3 p8615 otp 18- 3 table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p1.1 sdat 13 (*30) i/o serial data pin (output when reading, input when writing) input & push-pull output port can be assigned p1.0 sclk 12 (*29) i serial clock pin (input only pin) test v pp (test) 23 (*41) i eprom cell writing power supply pin (indicates otp mode entering) when writing 12.5 v is applied and when reading 5v is applied.(option) reset reset 35 (*9) i chip initialization v dd /v ss1 /v ss2 v dd /v ss /v ss 9 / 32 / 41 (*26 / 6 / 15) i logic power supply pin. v dd should be tied to 5 v during programming. note: * means the 44-qfp otp pin number. table 18-2. comparison of S3P8615 and s3c8618/c8615 features characteristic S3P8615 s3c8618/c8615 program memory 16 k byte eprom 16 k byte mask rom operating voltage (v dd ) 4.5 v to 5.5 v 4.5 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42-sdip, 44-qfp 42-sdip, 44-qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P8615, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15?a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P8615 otp s3c8618/c8615/p8615 18- 4 d.c. electrical characteristics table 18-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high leakage current i lih1 v in = v dd ; all input pins except x in , x out ? ? 3 a i lih2 v in = v dd ; x out only 20 i lih3 v in = v dd ; x in only 2.5 6 20 input low leakage current i lil1 v in = 0 v ; all input pins except x in , x out and reset ? ? ? 3 a i lil2 v in = 0 v ; x out only ? ? ? 20 i lil3 v in = 0 v ; x in only ? 2.5 ? 6 ? 20 output high leakage current i loh1 v out = v dd ? ? 3 a output low leakage current i lol 1 v out = 0 v ? ? ? 3 a supply current i dd1 normal operating mode; 12 mhz cpu clock ? 15 30 ma i dd2 idle mode ; 12 mhz cpu clock 5 1 0 i dd3 stop mode; v dd = 5.0 v ? 1 10 a data retention supply voltage v dddr stop mode 2 ? 6 v data retention supply voltage i dddr stop mode; v dddr = 2v ? ? 5 a
s3c8618/c8615/p8615 s3 p8615 otp 18- 5 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 18-3. otp programming algorithm

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